.include "tn2313def.inc"

.equ _1WDDR = DDRB
.equ _1WPIN = PINB
.equ _1WL   = PB4
.equ _1WPORT = PORTB

;rejestry
.def sregtmp  =r0
.def ZERO     =r1
.def minus    =r2
;r3
;r4
;r5
;r6
;r7
;r8
;r9
;r10
;r11
;r12
;r13
;r14
;r15

.def tmp      =r16
.def tmp1     =r17
.def tmpi     =r18
.def ARG      =r19
.def ARGL     =r19
.def ARGH     =r20
.def ARGD     =r21
.def temp10   =r22
.def temp1    =r23
.def temp01   =r24
.def tmp2     =r25
.def tmp3     =r26
;r27
;r28
;r29
.def ZL       =r30
.def ZH       =r31

;.macro adi
;	subi @0, 256-@1
;.endmacro

.dseg

.cseg
	ldi tmp, RAMEND		;stos
	out SPL, tmp
	ldi tmp, 1<<WGM01
	out TCCR0A, tmp
	ldi tmp, (1<<CS02)|(1<<CS00)
	out TCCR0B, tmp
	ser tmp
	out DDRD, tmp
	out DDRA, tmp
	ldi tmp, 0b10001111
	out DDRB, tmp
	clr ZERO
	rjmp main

vector_TM0A:
	in sregtmp, SREG
	push ARGD

	ldi tmpi, 200	;start rejestru timera
	out TCNT0, tmpi

	sbi PORTB, 1
	ldi tmpi, 5
	sbrc minus, 0
	ldi tmpi, 6
	rcall set_digit
;
	cpi temp10, 1
	brlo wygas
	sbi PORTB, 0
	wygas:
	mov tmpi, temp10
	rcall set_digit

	sbi PORTB, 3
	mov tmpi, temp1
	rcall set_digit
;
	sbi PORTB, 7
	mov tmpi, temp01
	rcall set_digit

	pop ARGD
	out SREG, sregtmp
	reti


main:
	ldi tmp, 1<<OCIE0A
	out TIMSK, tmp
;	sei
	loop:
		ldi ARG, 255
		rcall _delay_ms
		rcall wysw_temp
;		inc minus
;		inc temp01
;		cpi temp01, 10
;		brlo loop
;		clr temp01
;		inc temp1
;		cpi temp1, 10
;		brlo loop
;		clr temp1
;		inc temp10
;		cpi temp10, 10
;		brlo loop
;		clr temp10
	rjmp loop

set_digit:
	cpi tmpi, 10
	brsh op
	ldi ZL, low(tab_digit)
	ldi ZH, high(tab_digit)
	add tmpi, tmpi
	add ZL, tmpi
;	adc ZH, ZERO
	ijmp

tab_digit:
digit_0:
	sbi PORTA, 0
	rjmp op
digit_1:
	sbi PORTD, 2
	rjmp op
digit_2:
	sbi PORTD, 3
	rjmp op
digit_3:
	sbi PORTD, 4
	rjmp op
digit_4:
	sbi PORTD, 5
	rjmp op
digit_5:
	sbi PORTD, 6
	rjmp op
digit_6:
	sbi PORTB, 2
	rjmp op
digit_7:
	sbi PORTD, 0
	rjmp op
digit_8:
	sbi PORTD, 1
	rjmp op
digit_9:
	sbi PORTA, 1

op:
	ldi ARGD, 255
	rcall _delay_us
	ldi ARGD, 255
	rcall _delay_us
	ldi ARGD, 255
	rcall _delay_us
	in tmpi, PORTB
	andi tmpi, 1<<_1WL
	out PORTA, ZERO
	out PORTB, tmpi
	out PORTD, ZERO
	ldi ARGD, 180
	rcall _delay_us
	ret

wysw_temp:
	rcall _1wire_init	;odczyt i konwersja
	ldi ARG, 0xCC
	rcall _1wire_write
	ldi ARG, 0x44
	rcall _1wire_write
	sbi _1WPORT, _1WL	;zasilanie 'parasite'
	sbi _1WDDR, _1WL
	sei
	ldi ARG, 255
	rcall _delay_ms
	ldi ARG, 255
	rcall _delay_ms
	ldi ARG, 255
	rcall _delay_ms
	cbi _1WPORT, _1WL
	cbi _1WDDR, _1WL
	rcall _1wire_init
	ldi ARG, 0xCC
	rcall _1wire_write
	ldi ARG, 0xBE
	rcall _1wire_write
	sei
	rcall _1wire_read
	push ARG
	rcall _1wire_read

	pop tmp
	mov tmp1, tmp
	ldi tmp2, 0b01010000
	eor tmp1, tmp2
	brne conv_continue
	mov tmp1, ARG
	ldi tmp2, 0b00000101
	eor tmp1, tmp2
	brne conv_continue
	ret

	conv_continue:

	bst ARG, 7
	bld minus, 0
	mov temp01, tmp

	brtc not_negative
	com ARG
	neg temp01
	
	not_negative:
	mov tmp1, temp01   ;stopnie beda w ARG
	andi tmp1, 0xf0
	or ARG, tmp1
	swap ARG

	andi temp01, 0x0f  ;dziesiate beda w temp01
	add temp01, temp01
	mov tmp1, temp01
	add temp01, temp01
	add temp01, temp01
	add temp01, tmp1
	swap temp01
	andi temp01, 0x0f

	rcall divmod
	mov temp10, ARGH
	mov temp1, ARGL
	ret

_delay_ms:
	delay_loop:
		ldi ARGD, 255
		rcall _delay_us
		ldi ARGD, 255
		rcall _delay_us
		ldi ARGD, 255
		rcall _delay_us
		ldi ARGD, 235
		rcall _delay_us
		dec ARG
	brne delay_loop
	ret

_delay_us:
	cpi ARGD, 0
	brne cz
	ldi ARGD, 60
	cz:
		nop
		nop
		nop
		nop
		nop
		dec ARGD
	brne cz
	ret

_1wire_init:
	cli
	sbi _1WDDR, _1WL
	ldi ARG, 1
	rcall _delay_ms
	cbi _1WDDR, _1WL
	rcall _delay_us
	sei
	ldi ARG, 1
	rcall _delay_ms
	ret

_1wire_write:
	ldi tmp, 8
	_write_loop:
		cli
		sbi _1WDDR, _1WL
		ldi ARGD, 1
		rcall _delay_us
		sbrc ARG, 0
		cbi _1WDDR, _1WL
		rcall _delay_us
		cbi _1WDDR, _1WL

		dec tmp
		breq _write_finish
		sei
		lsr ARG
	rjmp _write_loop
	_write_finish:
	ret

_1wire_read:
	clr ARG
	ldi tmp, 1
	_read_loop:
		cli
		sbi _1WDDR, _1WL
		ldi ARGD, 1
		rcall _delay_us
		cbi _1WDDR, _1WL
		ldi ARGD, 14
		rcall _delay_us
		sbic _1WPIN, _1WL
		or ARG, tmp
		sei
		rcall _delay_us

		lsl tmp
	brne _read_loop
	ret

divmod: ;wej: ARGL, wyj mod: ARGL, wyj div: ARGH
	clr ARGH
	div_loop:
		cpi ARGL, 10
		brlo div_finish
		inc ARGH
		subi ARGL, 10
	rjmp div_loop
	div_finish:
	ret