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+;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
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+;***** Created: 2006-07-05 11:07 ******* Source: ATtiny2313.xml **********
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+;*************************************************************************
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+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
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+;*
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+;* Number : AVR000
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+;* File Name : "tn2313def.inc"
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+;* Title : Register/Bit Definitions for the ATtiny2313
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+;* Date : 2006-07-05
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+;* Version : 2.23
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+;* Support E-mail : avr@atmel.com
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+;* Target MCU : ATtiny2313
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+;*
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+;* DESCRIPTION
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+;* When including this file in the assembly program file, all I/O register
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+;* names and I/O register bit names appearing in the data book can be used.
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+;* In addition, the six registers forming the three data pointers X, Y and
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+;* Z have been assigned names XL - ZH. Highest RAM address for Internal
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+;* SRAM is also defined
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+;*
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+;* The Register names are represented by their hexadecimal address.
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+;*
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+;* The Register Bit names are represented by their bit number (0-7).
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+;*
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+;* Please observe the difference in using the bit names with instructions
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+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
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+;* (skip if bit in register set/cleared). The following example illustrates
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+;* this:
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+;*
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+;* in r16,PORTB ;read PORTB latch
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+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
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+;* out PORTB,r16 ;output to PORTB
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+;*
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+;* in r16,TIFR ;read the Timer Interrupt Flag Register
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+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
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+;* rjmp TOV0_is_set ;jump if set
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+;* ... ;otherwise do something else
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+;*************************************************************************
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+
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+; ***** SPECIFY DEVICE ***************************************************
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+.device attiny2313
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+.equ SIGNATURE_000 = 0x1e
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+.equ SIGNATURE_001 = 0x91
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+.equ SIGNATURE_002 = 0x0a
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+
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+
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+; ***** I/O REGISTER DEFINITIONS *****************************************
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+; NOTE:
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+; Definitions marked "MEMORY MAPPED"are extended I/O ports
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+; and cannot be used with IN/OUT instructions
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+.equ SREG = 0x3f
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+.equ SPL = 0x3d
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+.equ OCR0B = 0x3c
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+.equ GIMSK = 0x3b
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+.equ EIFR = 0x3a
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+.equ TIMSK = 0x39
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+.equ TIFR = 0x38
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+.equ SPMCSR = 0x37
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+.equ OCR0A = 0x36
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+.equ MCUCR = 0x35
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+.equ MCUSR = 0x34
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+.equ TCCR0B = 0x33
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+.equ TCNT0 = 0x32
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+.equ OSCCAL = 0x31
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+.equ TCCR0A = 0x30
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+.equ TCCR1A = 0x2f
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+.equ TCCR1B = 0x2e
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+.equ TCNT1L = 0x2c
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+.equ TCNT1H = 0x2d
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+.equ OCR1AL = 0x2a
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+.equ OCR1AH = 0x2b
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+.equ OCR1BL = 0x28
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+.equ OCR1BH = 0x29
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+.equ CLKPR = 0x26
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+.equ ICR1L = 0x24
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+.equ ICR1H = 0x25
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+.equ GTCCR = 0x23
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+.equ TCCR1C = 0x22
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+.equ WDTCR = 0x21
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+.equ PCMSK = 0x20
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+.equ EEAR = 0x1e
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+.equ EEDR = 0x1d
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+.equ EECR = 0x1c
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+.equ PORTA = 0x1b
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+.equ DDRA = 0x1a
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+.equ PINA = 0x19
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+.equ PORTB = 0x18
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+.equ DDRB = 0x17
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+.equ PINB = 0x16
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+.equ GPIOR2 = 0x15
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+.equ GPIOR1 = 0x14
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+.equ GPIOR0 = 0x13
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+.equ PORTD = 0x12
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+.equ DDRD = 0x11
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+.equ PIND = 0x10
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+.equ USIDR = 0x0f
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+.equ USISR = 0x0e
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+.equ USICR = 0x0d
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+.equ UDR = 0x0c
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+.equ UCSRA = 0x0b
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+.equ UCSRB = 0x0a
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+.equ UBRRL = 0x09
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+.equ ACSR = 0x08
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+.equ UCSRC = 0x03
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+.equ UBRRH = 0x02
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+.equ DIDR = 0x01
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+
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+
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+; ***** BIT DEFINITIONS **************************************************
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+
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+; ***** PORTB ************************
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+; PORTB - Port B Data Register
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+.equ PORTB0 = 0 ; Port B Data Register bit 0
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+.equ PB0 = 0 ; For compatibility
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+.equ PORTB1 = 1 ; Port B Data Register bit 1
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+.equ PB1 = 1 ; For compatibility
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+.equ PORTB2 = 2 ; Port B Data Register bit 2
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+.equ PB2 = 2 ; For compatibility
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+.equ PORTB3 = 3 ; Port B Data Register bit 3
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+.equ PB3 = 3 ; For compatibility
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+.equ PORTB4 = 4 ; Port B Data Register bit 4
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+.equ PB4 = 4 ; For compatibility
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+.equ PORTB5 = 5 ; Port B Data Register bit 5
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+.equ PB5 = 5 ; For compatibility
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+.equ PORTB6 = 6 ; Port B Data Register bit 6
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+.equ PB6 = 6 ; For compatibility
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+.equ PORTB7 = 7 ; Port B Data Register bit 7
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+.equ PB7 = 7 ; For compatibility
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+
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+; DDRB - Port B Data Direction Register
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+.equ DDB0 = 0 ; Port B Data Direction Register bit 0
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+.equ DDB1 = 1 ; Port B Data Direction Register bit 1
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+.equ DDB2 = 2 ; Port B Data Direction Register bit 2
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+.equ DDB3 = 3 ; Port B Data Direction Register bit 3
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+.equ DDB4 = 4 ; Port B Data Direction Register bit 4
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+.equ DDB5 = 5 ; Port B Data Direction Register bit 5
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+.equ DDB6 = 6 ; Port B Data Direction Register bit 6
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+.equ DDB7 = 7 ; Port B Data Direction Register bit 7
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+
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+; PINB - Port B Input Pins
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+.equ PINB0 = 0 ; Port B Input Pins bit 0
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+.equ PINB1 = 1 ; Port B Input Pins bit 1
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+.equ PINB2 = 2 ; Port B Input Pins bit 2
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+.equ PINB3 = 3 ; Port B Input Pins bit 3
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+.equ PINB4 = 4 ; Port B Input Pins bit 4
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+.equ PINB5 = 5 ; Port B Input Pins bit 5
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+.equ PINB6 = 6 ; Port B Input Pins bit 6
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+.equ PINB7 = 7 ; Port B Input Pins bit 7
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+
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+
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+; ***** TIMER_COUNTER_0 **************
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+; TIMSK - Timer/Counter Interrupt Mask Register
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+.equ OCIE0A = 0 ; Timer/Counter0 Output Compare Match A Interrupt Enable
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+.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable
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+.equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable
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+
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+; TIFR - Timer/Counter Interrupt Flag register
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+.equ OCF0A = 0 ; Timer/Counter0 Output Compare Flag 0A
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+.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag
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+.equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B
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+
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+; OCR0B - Timer/Counter0 Output Compare Register
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+.equ OCR0_0 = 0 ;
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+.equ OCR0_1 = 1 ;
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+.equ OCR0_2 = 2 ;
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+.equ OCR0_3 = 3 ;
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+.equ OCR0_4 = 4 ;
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+.equ OCR0_5 = 5 ;
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+.equ OCR0_6 = 6 ;
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+.equ OCR0_7 = 7 ;
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+
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+; OCR0A - Timer/Counter0 Output Compare Register
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+;.equ OCR0_0 = 0 ;
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+;.equ OCR0_1 = 1 ;
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+;.equ OCR0_2 = 2 ;
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+;.equ OCR0_3 = 3 ;
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+;.equ OCR0_4 = 4 ;
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+;.equ OCR0_5 = 5 ;
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+;.equ OCR0_6 = 6 ;
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+;.equ OCR0_7 = 7 ;
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+
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+; TCCR0A - Timer/Counter Control Register A
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+.equ WGM00 = 0 ; Waveform Generation Mode
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+.equ WGM01 = 1 ; Waveform Generation Mode
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+.equ COM0B0 = 4 ; Compare Match Output B Mode
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+.equ COM0B1 = 5 ; Compare Match Output B Mode
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+.equ COM0A0 = 6 ; Compare Match Output A Mode
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+.equ COM0A1 = 7 ; Compare Match Output A Mode
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+
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+; TCNT0 - Timer/Counter0
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+.equ TCNT0_0 = 0 ;
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+.equ TCNT0_1 = 1 ;
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+.equ TCNT0_2 = 2 ;
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+.equ TCNT0_3 = 3 ;
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+.equ TCNT0_4 = 4 ;
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+.equ TCNT0_5 = 5 ;
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+.equ TCNT0_6 = 6 ;
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+.equ TCNT0_7 = 7 ;
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+
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+; TCCR0B - Timer/Counter Control Register B
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+.equ TCCR0 = TCCR0B ; For compatibility
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+.equ CS00 = 0 ; Clock Select
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+.equ CS01 = 1 ; Clock Select
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+.equ CS02 = 2 ; Clock Select
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+.equ WGM02 = 3 ;
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+.equ FOC0B = 6 ; Force Output Compare B
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+.equ FOC0A = 7 ; Force Output Compare B
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+
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+
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+; ***** TIMER_COUNTER_1 **************
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+; TIMSK - Timer/Counter Interrupt Mask Register
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+.equ ICIE1 = 3 ; Timer/Counter1 Input Capture Interrupt Enable
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+.equ TICIE = ICIE1 ; For compatibility
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+.equ OCIE1B = 5 ; Timer/Counter1 Output CompareB Match Interrupt Enable
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+.equ OCIE1A = 6 ; Timer/Counter1 Output CompareA Match Interrupt Enable
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+.equ TOIE1 = 7 ; Timer/Counter1 Overflow Interrupt Enable
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+
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+; TIFR - Timer/Counter Interrupt Flag register
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+.equ ICF1 = 3 ; Input Capture Flag 1
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+.equ OCF1B = 5 ; Output Compare Flag 1B
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+.equ OCF1A = 6 ; Output Compare Flag 1A
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+.equ TOV1 = 7 ; Timer/Counter1 Overflow Flag
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+
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+; TCCR1A - Timer/Counter1 Control Register A
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+.equ WGM10 = 0 ; Pulse Width Modulator Select Bit 0
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+.equ PWM10 = WGM10 ; For compatibility
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+.equ WGM11 = 1 ; Pulse Width Modulator Select Bit 1
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+.equ PWM11 = WGM11 ; For compatibility
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+.equ COM1B0 = 4 ; Comparet Ouput Mode 1B, bit 0
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+.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1
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+.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0
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+.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
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+
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+; TCCR1B - Timer/Counter1 Control Register B
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+.equ CS10 = 0 ; Clock Select bit 0
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+.equ CS11 = 1 ; Clock Select 1 bit 1
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+.equ CS12 = 2 ; Clock Select1 bit 2
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+.equ WGM12 = 3 ; Waveform Generation Mode Bit 2
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+.equ CTC1 = WGM12 ; For compatibility
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+.equ WGM13 = 4 ; Waveform Generation Mode Bit 3
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+.equ ICES1 = 6 ; Input Capture 1 Edge Select
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+.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
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+
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+; TCCR1C - Timer/Counter1 Control Register C
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+.equ FOC1B = 6 ; Force Output Compare for Channel B
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+.equ FOC1A = 7 ; Force Output Compare for Channel A
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+
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+
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+; ***** WATCHDOG *********************
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+; WDTCR - Watchdog Timer Control Register
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+.equ WDTCSR = WDTCR ; For compatibility
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+.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
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+.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
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+.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
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+.equ WDE = 3 ; Watch Dog Enable
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+.equ WDCE = 4 ; Watchdog Change Enable
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+.equ WDTOE = WDCE ; For compatibility
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+.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3
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+.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable
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+.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag
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+
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+
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+; ***** EXTERNAL_INTERRUPT ***********
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+; GIMSK - General Interrupt Mask Register
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+.equ PCIE = 5 ;
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+.equ INT0 = 6 ; External Interrupt Request 0 Enable
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+.equ INT1 = 7 ; External Interrupt Request 1 Enable
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+
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+; EIFR - Extended Interrupt Flag Register
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+.equ GIFR = EIFR ; For compatibility
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+.equ PCIF = 5 ;
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+.equ INTF0 = 6 ; External Interrupt Flag 0
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+.equ INTF1 = 7 ; External Interrupt Flag 1
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+
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+
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+; ***** USART ************************
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+; UDR - USART I/O Data Register
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+.equ UDR0 = 0 ; USART I/O Data Register bit 0
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+.equ UDR1 = 1 ; USART I/O Data Register bit 1
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+.equ UDR2 = 2 ; USART I/O Data Register bit 2
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+.equ UDR3 = 3 ; USART I/O Data Register bit 3
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+.equ UDR4 = 4 ; USART I/O Data Register bit 4
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+.equ UDR5 = 5 ; USART I/O Data Register bit 5
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+.equ UDR6 = 6 ; USART I/O Data Register bit 6
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+.equ UDR7 = 7 ; USART I/O Data Register bit 7
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+
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+; UCSRA - USART Control and Status Register A
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+.equ USR = UCSRA ; For compatibility
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+.equ MPCM = 0 ; Multi-processor Communication Mode
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+.equ U2X = 1 ; Double the USART Transmission Speed
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+.equ UPE = 2 ; USART Parity Error
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+.equ PE = UPE ; For compatibility
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+.equ DOR = 3 ; Data overRun
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+.equ FE = 4 ; Framing Error
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+.equ UDRE = 5 ; USART Data Register Empty
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+.equ TXC = 6 ; USART Transmitt Complete
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+.equ RXC = 7 ; USART Receive Complete
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+
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+; UCSRB - USART Control and Status Register B
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+.equ UCR = UCSRB ; For compatibility
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+.equ TXB8 = 0 ; Transmit Data Bit 8
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+.equ RXB8 = 1 ; Receive Data Bit 8
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+.equ UCSZ2 = 2 ; Character Size
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+.equ CHR9 = UCSZ2 ; For compatibility
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+.equ TXEN = 3 ; Transmitter Enable
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+.equ RXEN = 4 ; Receiver Enable
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+.equ UDRIE = 5 ; USART Data register Empty Interrupt Enable
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+.equ TXCIE = 6 ; TX Complete Interrupt Enable
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+.equ RXCIE = 7 ; RX Complete Interrupt Enable
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+
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+; UCSRC - USART Control and Status Register C
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+.equ UCPOL = 0 ; Clock Polarity
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+.equ UCSZ0 = 1 ; Character Size Bit 0
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+.equ UCSZ1 = 2 ; Character Size Bit 1
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+.equ USBS = 3 ; Stop Bit Select
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+.equ UPM0 = 4 ; Parity Mode Bit 0
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+.equ UPM1 = 5 ; Parity Mode Bit 1
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+.equ UMSEL = 6 ; USART Mode Select
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+
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+.equ UBRR = UBRRL ; For compatibility
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+
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+; ***** ANALOG_COMPARATOR ************
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+; ACSR - Analog Comparator Control And Status Register
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+.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
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+.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
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+.equ ACIC = 2 ;
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+.equ ACIE = 3 ; Analog Comparator Interrupt Enable
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+.equ ACI = 4 ; Analog Comparator Interrupt Flag
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+.equ ACO = 5 ; Analog Compare Output
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+.equ ACBG = 6 ; Analog Comparator Bandgap Select
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+.equ ACD = 7 ; Analog Comparator Disable
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+
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+; DIDR - Digital Input Disable Register 1
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+.equ AIN0D = 0 ; AIN0 Digital Input Disable
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+.equ AIN1D = 1 ; AIN1 Digital Input Disable
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+
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+
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+; ***** PORTD ************************
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+; PORTD - Data Register, Port D
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+.equ PORTD0 = 0 ;
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+.equ PD0 = 0 ; For compatibility
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+.equ PORTD1 = 1 ;
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+.equ PD1 = 1 ; For compatibility
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+.equ PORTD2 = 2 ;
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+.equ PD2 = 2 ; For compatibility
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+.equ PORTD3 = 3 ;
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+.equ PD3 = 3 ; For compatibility
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+.equ PORTD4 = 4 ;
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+.equ PD4 = 4 ; For compatibility
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+.equ PORTD5 = 5 ;
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+.equ PD5 = 5 ; For compatibility
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+.equ PORTD6 = 6 ;
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+.equ PD6 = 6 ; For compatibility
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+
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+; DDRD
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+.equ DDD0 = 0 ;
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+.equ DDD1 = 1 ;
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+.equ DDD2 = 2 ;
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+.equ DDD3 = 3 ;
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+.equ DDD4 = 4 ;
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+.equ DDD5 = 5 ;
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+.equ DDD6 = 6 ;
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+
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+; PIND - Input Pins, Port D
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+.equ PIND0 = 0 ;
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+.equ PIND1 = 1 ;
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+.equ PIND2 = 2 ;
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+.equ PIND3 = 3 ;
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+.equ PIND4 = 4 ;
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+.equ PIND5 = 5 ;
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+.equ PIND6 = 6 ;
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+
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+
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+; ***** EEPROM ***********************
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+; EEAR - EEPROM Read/Write Access
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+.equ EEARL = EEAR ; For compatibility
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+.equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0
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+.equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1
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+.equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2
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+.equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3
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+.equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4
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+.equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5
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+.equ EEAR6 = 6 ; EEPROM Read/Write Access bit 6
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+
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+; EEDR - EEPROM Data Register
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+.equ EEDR0 = 0 ; EEPROM Data Register bit 0
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+.equ EEDR1 = 1 ; EEPROM Data Register bit 1
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+.equ EEDR2 = 2 ; EEPROM Data Register bit 2
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+.equ EEDR3 = 3 ; EEPROM Data Register bit 3
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+.equ EEDR4 = 4 ; EEPROM Data Register bit 4
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+.equ EEDR5 = 5 ; EEPROM Data Register bit 5
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+.equ EEDR6 = 6 ; EEPROM Data Register bit 6
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+.equ EEDR7 = 7 ; EEPROM Data Register bit 7
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+
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+; EECR - EEPROM Control Register
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+.equ EERE = 0 ; EEPROM Read Enable
|
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|
+.equ EEPE = 1 ; EEPROM Write Enable
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+.equ EEWE = EEPE ; For compatibility
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+.equ EEMPE = 2 ; EEPROM Master Write Enable
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+.equ EEMWE = EEMPE ; For compatibility
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|
+.equ EERIE = 3 ; EEProm Ready Interrupt Enable
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|
+.equ EEPM0 = 4 ;
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+.equ EEPM1 = 5 ;
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+
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+
|
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+; ***** PORTA ************************
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+; PORTA - Port A Data Register
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+.equ PORTA0 = 0 ; Port A Data Register bit 0
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+.equ PA0 = 0 ; For compatibility
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+.equ PORTA1 = 1 ; Port A Data Register bit 1
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+.equ PA1 = 1 ; For compatibility
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+.equ PORTA2 = 2 ; Port A Data Register bit 2
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+.equ PA2 = 2 ; For compatibility
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+
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+; DDRA - Port A Data Direction Register
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+.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0
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+.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1
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+.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2
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+
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+; PINA - Port A Input Pins
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+.equ PINA0 = 0 ; Input Pins, Port A bit 0
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+.equ PINA1 = 1 ; Input Pins, Port A bit 1
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+.equ PINA2 = 2 ; Input Pins, Port A bit 2
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+
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+
|
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+; ***** CPU **************************
|
|
|
+; SREG - Status Register
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+.equ SREG_C = 0 ; Carry Flag
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+.equ SREG_Z = 1 ; Zero Flag
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+.equ SREG_N = 2 ; Negative Flag
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+.equ SREG_V = 3 ; Two's Complement Overflow Flag
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+.equ SREG_S = 4 ; Sign Bit
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+.equ SREG_H = 5 ; Half Carry Flag
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+.equ SREG_T = 6 ; Bit Copy Storage
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+.equ SREG_I = 7 ; Global Interrupt Enable
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+
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+; SPMCSR - Store Program Memory Control and Status register
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+.equ SPMEN = 0 ; Store Program Memory Enable
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+.equ PGERS = 1 ; Page Erase
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+.equ PGWRT = 2 ; Page Write
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+.equ RFLB = 3 ; Read Fuse and Lock Bits
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+.equ CTPB = 4
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+
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+; MCUCR - MCU Control Register
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+.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0
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+.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1
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+.equ ISC10 = 2 ; Interrupt Sense Control 1 bit 0
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+.equ ISC11 = 3 ; Interrupt Sense Control 1 bit 1
|
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+.equ SM0 = 4 ; Sleep Mode Select Bit 0
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+.equ SM = SM0 ; For compatibility
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+.equ SE = 5 ; Sleep Enable
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+.equ SM1 = 6 ; Sleep Mode Select Bit 1
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|
|
+.equ PUD = 7 ; Pull-up Disable
|
|
|
+
|
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|
+; CLKPR - Clock Prescale Register
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+.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0
|
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+.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1
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+.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2
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+.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3
|
|
|
+.equ CLKPCE = 7 ; Clock Prescaler Change Enable
|
|
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+
|
|
|
+; MCUSR - MCU Status register
|
|
|
+.equ PORF = 0 ; Power-On Reset Flag
|
|
|
+.equ EXTRF = 1 ; External Reset Flag
|
|
|
+.equ BORF = 2 ; Brown-out Reset Flag
|
|
|
+.equ WDRF = 3 ; Watchdog Reset Flag
|
|
|
+
|
|
|
+; OSCCAL - Oscillator Calibration Register
|
|
|
+.equ CAL0 = 0 ; Oscillatro Calibration Value Bit 0
|
|
|
+.equ CAL1 = 1 ; Oscillatro Calibration Value Bit 1
|
|
|
+.equ CAL2 = 2 ; Oscillatro Calibration Value Bit 2
|
|
|
+.equ CAL3 = 3 ; Oscillatro Calibration Value Bit 3
|
|
|
+.equ CAL4 = 4 ; Oscillatro Calibration Value Bit 4
|
|
|
+.equ CAL5 = 5 ; Oscillatro Calibration Value Bit 5
|
|
|
+.equ CAL6 = 6 ; Oscillatro Calibration Value Bit 6
|
|
|
+
|
|
|
+; GTCCR - General Timer Counter Control Register
|
|
|
+.equ SFIOR = GTCCR ; For compatibility
|
|
|
+.equ PSR10 = 0 ;
|
|
|
+
|
|
|
+; PCMSK - Pin-Change Mask register
|
|
|
+.equ PCINT0 = 0 ; Pin-Change Interrupt 0
|
|
|
+.equ PCINT1 = 1 ; Pin-Change Interrupt 1
|
|
|
+.equ PCINT2 = 2 ; Pin-Change Interrupt 2
|
|
|
+.equ PCINT3 = 3 ; Pin-Change Interrupt 3
|
|
|
+.equ PCINT4 = 4 ; Pin-Change Interrupt 4
|
|
|
+.equ PCINT5 = 5 ; Pin-Change Interrupt 5
|
|
|
+.equ PCINT6 = 6 ; Pin-Change Interrupt 6
|
|
|
+.equ PCINT7 = 7 ; Pin-Change Interrupt 7
|
|
|
+
|
|
|
+; GPIOR2 - General Purpose I/O Register 2
|
|
|
+.equ GPIOR20 = 0 ; General Purpose I/O Register 2 bit 0
|
|
|
+.equ GPIOR21 = 1 ; General Purpose I/O Register 2 bit 1
|
|
|
+.equ GPIOR22 = 2 ; General Purpose I/O Register 2 bit 2
|
|
|
+.equ GPIOR23 = 3 ; General Purpose I/O Register 2 bit 3
|
|
|
+.equ GPIOR24 = 4 ; General Purpose I/O Register 2 bit 4
|
|
|
+.equ GPIOR25 = 5 ; General Purpose I/O Register 2 bit 5
|
|
|
+.equ GPIOR26 = 6 ; General Purpose I/O Register 2 bit 6
|
|
|
+.equ GPIOR27 = 7 ; General Purpose I/O Register 2 bit 7
|
|
|
+
|
|
|
+; GPIOR1 - General Purpose I/O Register 1
|
|
|
+.equ GPIOR10 = 0 ; General Purpose I/O Register 1 bit 0
|
|
|
+.equ GPIOR11 = 1 ; General Purpose I/O Register 1 bit 1
|
|
|
+.equ GPIOR12 = 2 ; General Purpose I/O Register 1 bit 2
|
|
|
+.equ GPIOR13 = 3 ; General Purpose I/O Register 1 bit 3
|
|
|
+.equ GPIOR14 = 4 ; General Purpose I/O Register 1 bit 4
|
|
|
+.equ GPIOR15 = 5 ; General Purpose I/O Register 1 bit 5
|
|
|
+.equ GPIOR16 = 6 ; General Purpose I/O Register 1 bit 6
|
|
|
+.equ GPIOR17 = 7 ; General Purpose I/O Register 1 bit 7
|
|
|
+
|
|
|
+; GPIOR0 - General Purpose I/O Register 0
|
|
|
+.equ GPIOR00 = 0 ; General Purpose I/O Register 0 bit 0
|
|
|
+.equ GPIOR01 = 1 ; General Purpose I/O Register 0 bit 1
|
|
|
+.equ GPIOR02 = 2 ; General Purpose I/O Register 0 bit 2
|
|
|
+.equ GPIOR03 = 3 ; General Purpose I/O Register 0 bit 3
|
|
|
+.equ GPIOR04 = 4 ; General Purpose I/O Register 0 bit 4
|
|
|
+.equ GPIOR05 = 5 ; General Purpose I/O Register 0 bit 5
|
|
|
+.equ GPIOR06 = 6 ; General Purpose I/O Register 0 bit 6
|
|
|
+.equ GPIOR07 = 7 ; General Purpose I/O Register 0 bit 7
|
|
|
+
|
|
|
+
|
|
|
+; ***** USI **************************
|
|
|
+; USIDR - USI Data Register
|
|
|
+.equ USIDR0 = 0 ; USI Data Register bit 0
|
|
|
+.equ USIDR1 = 1 ; USI Data Register bit 1
|
|
|
+.equ USIDR2 = 2 ; USI Data Register bit 2
|
|
|
+.equ USIDR3 = 3 ; USI Data Register bit 3
|
|
|
+.equ USIDR4 = 4 ; USI Data Register bit 4
|
|
|
+.equ USIDR5 = 5 ; USI Data Register bit 5
|
|
|
+.equ USIDR6 = 6 ; USI Data Register bit 6
|
|
|
+.equ USIDR7 = 7 ; USI Data Register bit 7
|
|
|
+
|
|
|
+; USISR - USI Status Register
|
|
|
+.equ USICNT0 = 0 ; USI Counter Value Bit 0
|
|
|
+.equ USICNT1 = 1 ; USI Counter Value Bit 1
|
|
|
+.equ USICNT2 = 2 ; USI Counter Value Bit 2
|
|
|
+.equ USICNT3 = 3 ; USI Counter Value Bit 3
|
|
|
+.equ USIDC = 4 ; Data Output Collision
|
|
|
+.equ USIPF = 5 ; Stop Condition Flag
|
|
|
+.equ USIOIF = 6 ; Counter Overflow Interrupt Flag
|
|
|
+.equ USISIF = 7 ; Start Condition Interrupt Flag
|
|
|
+
|
|
|
+; USICR - USI Control Register
|
|
|
+.equ USITC = 0 ; Toggle Clock Port Pin
|
|
|
+.equ USICLK = 1 ; Clock Strobe
|
|
|
+.equ USICS0 = 2 ; USI Clock Source Select Bit 0
|
|
|
+.equ USICS1 = 3 ; USI Clock Source Select Bit 1
|
|
|
+.equ USIWM0 = 4 ; USI Wire Mode Bit 0
|
|
|
+.equ USIWM1 = 5 ; USI Wire Mode Bit 1
|
|
|
+.equ USIOIE = 6 ; Counter Overflow Interrupt Enable
|
|
|
+.equ USISIE = 7 ; Start Condition Interrupt Enable
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+; ***** LOCKSBITS ********************************************************
|
|
|
+.equ LB1 = 0 ; Lockbit
|
|
|
+.equ LB2 = 1 ; Lockbit
|
|
|
+
|
|
|
+
|
|
|
+; ***** FUSES ************************************************************
|
|
|
+; LOW fuse bits
|
|
|
+.equ CKSEL0 = 0 ; Select Clock Source
|
|
|
+.equ CKSEL1 = 1 ; Select Clock Source
|
|
|
+.equ CKSEL2 = 2 ; Select Clock Source
|
|
|
+.equ CKSEL3 = 3 ; Select Clock Source
|
|
|
+.equ SUT0 = 4 ; Select start-up time
|
|
|
+.equ SUT1 = 5 ; Select start-up time
|
|
|
+.equ CKOUT = 6 ; Clock output
|
|
|
+.equ CKDIV8 = 7 ; Divide clock by 8
|
|
|
+
|
|
|
+; HIGH fuse bits
|
|
|
+.equ BODLEVEL0 = 0 ; Brown-out Detector trigger level
|
|
|
+.equ BODLEVEL1 = 1 ; Brown-out Detector trigger level
|
|
|
+.equ BODLEVEL2 = 2 ; Brown-out Detector trigger level
|
|
|
+.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase
|
|
|
+.equ WDTON = 4 ; Watchdog Timer Always On
|
|
|
+.equ SPIEN = 5 ; Enable Serial programming and Data Downloading
|
|
|
+.equ DWEN = 6 ; debugWIRE Enable
|
|
|
+.equ RSTDISBL = 7 ; External reset disable
|
|
|
+
|
|
|
+; EXTENDED fuse bits
|
|
|
+.equ SELFPRGEN = 0 ; Self Programming Enable
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+; ***** CPU REGISTER DEFINITIONS *****************************************
|
|
|
+.def XH = r27
|
|
|
+.def XL = r26
|
|
|
+.def YH = r29
|
|
|
+.def YL = r28
|
|
|
+.def ZH = r31
|
|
|
+.def ZL = r30
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+; ***** DATA MEMORY DECLARATIONS *****************************************
|
|
|
+.equ FLASHEND = 0x03ff ; Note: Word address
|
|
|
+.equ IOEND = 0x003f
|
|
|
+.equ SRAM_START = 0x0060
|
|
|
+.equ SRAM_SIZE = 128
|
|
|
+.equ RAMEND = 0x00df
|
|
|
+.equ XRAMEND = 0x0000
|
|
|
+.equ E2END = 0x007f
|
|
|
+.equ EEPROMEND = 0x007f
|
|
|
+.equ EEADRBITS = 7
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+; ***** BOOTLOADER DECLARATIONS ******************************************
|
|
|
+.equ NRWW_START_ADDR = 0x0
|
|
|
+.equ NRWW_STOP_ADDR = 0x3ff
|
|
|
+.equ RWW_START_ADDR = 0x0
|
|
|
+.equ RWW_STOP_ADDR = 0x0
|
|
|
+.equ PAGESIZE = 16
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+; ***** INTERRUPT VECTORS ************************************************
|
|
|
+.equ INT0addr = 0x0001 ; External Interrupt Request 0
|
|
|
+.equ INT1addr = 0x0002 ; External Interrupt Request 1
|
|
|
+.equ ICP1addr = 0x0003 ; Timer/Counter1 Capture Event
|
|
|
+.equ OC1Aaddr = 0x0004 ; Timer/Counter1 Compare Match A
|
|
|
+.equ OC1addr = 0x0004 ; For compatibility
|
|
|
+.equ OVF1addr = 0x0005 ; Timer/Counter1 Overflow
|
|
|
+.equ OVF0addr = 0x0006 ; Timer/Counter0 Overflow
|
|
|
+.equ URXCaddr = 0x0007 ; USART, Rx Complete
|
|
|
+.equ URXC0addr = 0x0007 ; For compatibility
|
|
|
+.equ UDREaddr = 0x0008 ; USART Data Register Empty
|
|
|
+.equ UDRE0addr = 0x0008 ; For compatibility
|
|
|
+.equ UTXCaddr = 0x0009 ; USART, Tx Complete
|
|
|
+.equ UTXC0addr = 0x0009 ; For compatibility
|
|
|
+.equ ACIaddr = 0x000a ; Analog Comparator
|
|
|
+.equ PCIaddr = 0x000b ;
|
|
|
+.equ OC1Baddr = 0x000c ;
|
|
|
+.equ OC0Aaddr = 0x000d ;
|
|
|
+.equ OC0Baddr = 0x000e ;
|
|
|
+.equ USI_STARTaddr = 0x000f ; USI Start Condition
|
|
|
+.equ USI_OVFaddr = 0x0010 ; USI Overflow
|
|
|
+.equ ERDYaddr = 0x0011 ;
|
|
|
+.equ WDTaddr = 0x0012 ; Watchdog Timer Overflow
|
|
|
+
|
|
|
+.equ INT_VECTORS_SIZE = 19 ; size in words
|
|
|
+
|
|
|
+; ***** END OF FILE ******************************************************
|
|
|
+
|
k4be
1 tydzień temu