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mmc.c 14 KB

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  1. /*-----------------------------------------------------------------------*/
  2. /* MMCv3/SDv1/SDv2 (in SPI mode) control module (C)ChaN, 2012 */
  3. /*-----------------------------------------------------------------------*/
  4. #include <avr/io.h>
  5. #include "ff.h"
  6. #include "diskio.h"
  7. #include "main.h"
  8. /* Port controls (Platform dependent) */
  9. #define CS_LOW() {SD_CS_PORT &= ~SD_CS; LEDR_ON();} /* CS=low, LED on */
  10. #define CS_HIGH() {SD_CS_PORT |= SD_CS; LEDR_OFF();} /* CS=high, LED off */
  11. #define POWER_ON() {SD_PWROFF_PORT &= ~SD_PWROFF;} /* MMC power on */
  12. #define POWER_OFF() {SD_PWROFF_PORT |= SD_PWROFF;} /* MMC power off */
  13. #define POWER (!(SD_PWROFF_PIN & SD_PWROFF)) /* Test for power state. on:true, off:false */
  14. #define SOCKINS (!(SD_CD_PIN & SD_CD)) /* Test for card exist. yes:true, true:false, default:true */
  15. #define SOCKWP (SD_WP_PIN & SD_WP) /* Test for write protect. yes:true, no:false, default:false */
  16. #define FCLK_SLOW() SPCR = _BV(MSTR) | _BV(SPE) | _BV(SPR1) | _BV(SPR0) /* Set slow clock (F_CPU / 64) */
  17. #define FCLK_FAST() SPCR = _BV(MSTR) | _BV(SPE) /* Set fast clock (F_CPU / 2) */
  18. /*--------------------------------------------------------------------------
  19. Module Private Functions
  20. ---------------------------------------------------------------------------*/
  21. /* Definitions for MMC/SDC command */
  22. #define CMD0 (0) /* GO_IDLE_STATE */
  23. #define CMD1 (1) /* SEND_OP_COND (MMC) */
  24. #define ACMD41 (0x80+41) /* SEND_OP_COND (SDC) */
  25. #define CMD8 (8) /* SEND_IF_COND */
  26. #define CMD9 (9) /* SEND_CSD */
  27. #define CMD10 (10) /* SEND_CID */
  28. #define CMD12 (12) /* STOP_TRANSMISSION */
  29. #define ACMD13 (0x80+13) /* SD_STATUS (SDC) */
  30. #define CMD16 (16) /* SET_BLOCKLEN */
  31. #define CMD17 (17) /* READ_SINGLE_BLOCK */
  32. #define CMD18 (18) /* READ_MULTIPLE_BLOCK */
  33. #define CMD23 (23) /* SET_BLOCK_COUNT (MMC) */
  34. #define ACMD23 (0x80+23) /* SET_WR_BLK_ERASE_COUNT (SDC) */
  35. #define CMD24 (24) /* WRITE_BLOCK */
  36. #define CMD25 (25) /* WRITE_MULTIPLE_BLOCK */
  37. #define CMD55 (55) /* APP_CMD */
  38. #define CMD58 (58) /* READ_OCR */
  39. /* Card type flags (CardType) */
  40. #define CT_MMC 0x01 /* MMC ver 3 */
  41. #define CT_SD1 0x02 /* SD ver 1 */
  42. #define CT_SD2 0x04 /* SD ver 2 */
  43. #define CT_SDC (CT_SD1|CT_SD2) /* SD */
  44. #define CT_BLOCK 0x08 /* Block addressing */
  45. static volatile
  46. DSTATUS Stat = STA_NOINIT; /* Disk status */
  47. static volatile
  48. BYTE Timer1, Timer2; /* 100Hz decrement timer */
  49. static
  50. BYTE CardType; /* Card type flags */
  51. /*-----------------------------------------------------------------------*/
  52. /* Power Control (Platform dependent) */
  53. /*-----------------------------------------------------------------------*/
  54. /* When the target system does not support socket power control, there */
  55. /* is nothing to do in these functions and chk_power always returns 1. */
  56. static
  57. void power_off (void)
  58. {
  59. SPCR = 0; /* Disable SPI function */
  60. DDRB &= ~(_BV(PB5) | _BV(PB7)); /* Set SCK/MOSI to hi-z */
  61. SD_CS_DDR &= ~SD_CS;
  62. POWER_OFF();
  63. Stat |= STA_NOINIT;
  64. }
  65. static
  66. void power_on (void) /* Apply power sequence */
  67. {
  68. SD_PWROFF_DDR |= SD_PWROFF;
  69. for (Timer1 = 30; Timer1; ) {}; /* 300ms */
  70. POWER_ON(); /* Power on */
  71. for (Timer1 = 3; Timer1; ) {}; /* 30ms */
  72. SD_CS_PORT |= SD_CS;
  73. SD_CS_DDR |= SD_CS;
  74. PORTB |= _BV(PB5) | _BV(PB7); /* Configure SCK/MOSI as output */
  75. DDRB |= _BV(PB5) | _BV(PB7);
  76. FCLK_SLOW(); /* Enable SPI function in mode 0 */
  77. SPSR = _BV(SPI2X); /* SPI 2x mode */
  78. }
  79. /*-----------------------------------------------------------------------*/
  80. /* Transmit/Receive data from/to MMC via SPI (Platform dependent) */
  81. /*-----------------------------------------------------------------------*/
  82. /* Exchange a byte */
  83. static
  84. BYTE xchg_spi ( /* Returns received data */
  85. BYTE dat /* Data to be sent */
  86. )
  87. {
  88. SPDR = dat;
  89. loop_until_bit_is_set(SPSR, SPIF);
  90. return SPDR;
  91. }
  92. /* Send a data block */
  93. static
  94. void xmit_spi_multi (
  95. const BYTE *p, /* Data block to be sent */
  96. UINT cnt /* Size of data block */
  97. )
  98. {
  99. do {
  100. SPDR = *p++; loop_until_bit_is_set(SPSR,SPIF);
  101. SPDR = *p++; loop_until_bit_is_set(SPSR,SPIF);
  102. } while (cnt -= 2);
  103. }
  104. /* Receive a data block */
  105. static
  106. void rcvr_spi_multi (
  107. BYTE *p, /* Data buffer */
  108. UINT cnt /* Size of data block */
  109. )
  110. {
  111. do {
  112. SPDR = 0xFF; loop_until_bit_is_set(SPSR,SPIF); *p++ = SPDR;
  113. SPDR = 0xFF; loop_until_bit_is_set(SPSR,SPIF); *p++ = SPDR;
  114. } while (cnt -= 2);
  115. }
  116. /*-----------------------------------------------------------------------*/
  117. /* Wait for card ready */
  118. /*-----------------------------------------------------------------------*/
  119. static
  120. int wait_ready (void) /* 1:OK, 0:Timeout */
  121. {
  122. BYTE d;
  123. Timer2 = 50; /* Wait for ready in timeout of 500ms */
  124. do
  125. d = xchg_spi(0xFF);
  126. while (d != 0xFF && Timer2);
  127. return (d == 0xFF) ? 1 : 0;
  128. }
  129. /*-----------------------------------------------------------------------*/
  130. /* Deselect the card and release SPI bus */
  131. /*-----------------------------------------------------------------------*/
  132. static
  133. void deselect (void)
  134. {
  135. CS_HIGH();
  136. xchg_spi(0xFF); /* Dummy clock (force DO hi-z for multiple slave SPI) */
  137. }
  138. /*-----------------------------------------------------------------------*/
  139. /* Select the card and wait for ready */
  140. /*-----------------------------------------------------------------------*/
  141. static
  142. int select (void) /* 1:Successful, 0:Timeout */
  143. {
  144. CS_LOW();
  145. xchg_spi(0xFF); /* Dummy clock (force DO enabled) */
  146. if (wait_ready()) return 1; /* OK */
  147. deselect();
  148. return 0; /* Timeout */
  149. }
  150. /*-----------------------------------------------------------------------*/
  151. /* Receive a data packet from MMC */
  152. /*-----------------------------------------------------------------------*/
  153. static
  154. int rcvr_datablock (
  155. BYTE *buff, /* Data buffer to store received data */
  156. UINT btr /* Byte count (must be multiple of 4) */
  157. )
  158. {
  159. BYTE token;
  160. Timer1 = 20;
  161. do { /* Wait for data packet in timeout of 200ms */
  162. token = xchg_spi(0xFF);
  163. } while ((token == 0xFF) && Timer1);
  164. if (token != 0xFE) return 0; /* If not valid data token, retutn with error */
  165. rcvr_spi_multi(buff, btr); /* Receive the data block into buffer */
  166. xchg_spi(0xFF); /* Discard CRC */
  167. xchg_spi(0xFF);
  168. return 1; /* Return with success */
  169. }
  170. /*-----------------------------------------------------------------------*/
  171. /* Send a data packet to MMC */
  172. /*-----------------------------------------------------------------------*/
  173. static
  174. int xmit_datablock (
  175. const BYTE *buff, /* 512 byte data block to be transmitted */
  176. BYTE token /* Data/Stop token */
  177. )
  178. {
  179. BYTE resp;
  180. if (!wait_ready()) return 0;
  181. xchg_spi(token); /* Xmit data token */
  182. if (token != 0xFD) { /* Is data token */
  183. xmit_spi_multi(buff, 512); /* Xmit the data block to the MMC */
  184. xchg_spi(0xFF); /* CRC (Dummy) */
  185. xchg_spi(0xFF);
  186. resp = xchg_spi(0xFF); /* Reveive data response */
  187. if ((resp & 0x1F) != 0x05) /* If not accepted, return with error */
  188. return 0;
  189. }
  190. return 1;
  191. }
  192. /*-----------------------------------------------------------------------*/
  193. /* Send a command packet to MMC */
  194. /*-----------------------------------------------------------------------*/
  195. static
  196. BYTE send_cmd ( /* Returns R1 resp (bit7==1:Send failed) */
  197. BYTE cmd, /* Command index */
  198. DWORD arg /* Argument */
  199. )
  200. {
  201. BYTE n, res;
  202. if (cmd & 0x80) { /* ACMD<n> is the command sequense of CMD55-CMD<n> */
  203. cmd &= 0x7F;
  204. res = send_cmd(CMD55, 0);
  205. if (res > 1) return res;
  206. }
  207. /* Select the card and wait for ready */
  208. deselect();
  209. if (!select()) return 0xFF;
  210. /* Send command packet */
  211. xchg_spi(0x40 | cmd); /* Start + Command index */
  212. xchg_spi((BYTE)(arg >> 24)); /* Argument[31..24] */
  213. xchg_spi((BYTE)(arg >> 16)); /* Argument[23..16] */
  214. xchg_spi((BYTE)(arg >> 8)); /* Argument[15..8] */
  215. xchg_spi((BYTE)arg); /* Argument[7..0] */
  216. n = 0x01; /* Dummy CRC + Stop */
  217. if (cmd == CMD0) n = 0x95; /* Valid CRC for CMD0(0) + Stop */
  218. if (cmd == CMD8) n = 0x87; /* Valid CRC for CMD8(0x1AA) Stop */
  219. xchg_spi(n);
  220. /* Receive command response */
  221. if (cmd == CMD12) xchg_spi(0xFF); /* Skip a stuff byte when stop reading */
  222. n = 10; /* Wait for a valid response in timeout of 10 attempts */
  223. do
  224. res = xchg_spi(0xFF);
  225. while ((res & 0x80) && --n);
  226. return res; /* Return with the response value */
  227. }
  228. /*--------------------------------------------------------------------------
  229. Public Functions
  230. ---------------------------------------------------------------------------*/
  231. /*-----------------------------------------------------------------------*/
  232. /* Initialize Disk Drive */
  233. /*-----------------------------------------------------------------------*/
  234. DSTATUS disk_initialize (
  235. BYTE drv /* Physical drive nmuber (0) */
  236. )
  237. {
  238. BYTE n, cmd, ty, ocr[4];
  239. if (drv) return STA_NOINIT; /* Supports only single drive */
  240. power_off(); /* Turn off the socket power to reset the card */
  241. if (Stat & STA_NODISK) return Stat; /* No card in the socket */
  242. power_on(); /* Turn on the socket power */
  243. FCLK_SLOW();
  244. for (n = 10; n; n--) xchg_spi(0xFF); /* 80 dummy clocks */
  245. ty = 0;
  246. if (send_cmd(CMD0, 0) == 1) { /* Enter Idle state */
  247. Timer1 = 100; /* Initialization timeout of 1000 msec */
  248. if (send_cmd(CMD8, 0x1AA) == 1) { /* SDv2? */
  249. for (n = 0; n < 4; n++) ocr[n] = xchg_spi(0xFF); /* Get trailing return value of R7 resp */
  250. if (ocr[2] == 0x01 && ocr[3] == 0xAA) { /* The card can work at vdd range of 2.7-3.6V */
  251. while (Timer1 && send_cmd(ACMD41, 1UL << 30)); /* Wait for leaving idle state (ACMD41 with HCS bit) */
  252. if (Timer1 && send_cmd(CMD58, 0) == 0) { /* Check CCS bit in the OCR */
  253. for (n = 0; n < 4; n++) ocr[n] = xchg_spi(0xFF);
  254. ty = (ocr[0] & 0x40) ? CT_SD2 | CT_BLOCK : CT_SD2; /* SDv2 */
  255. }
  256. }
  257. } else { /* SDv1 or MMCv3 */
  258. if (send_cmd(ACMD41, 0) <= 1) {
  259. ty = CT_SD1; cmd = ACMD41; /* SDv1 */
  260. } else {
  261. ty = CT_MMC; cmd = CMD1; /* MMCv3 */
  262. }
  263. while (Timer1 && send_cmd(cmd, 0)); /* Wait for leaving idle state */
  264. if (!Timer1 || send_cmd(CMD16, 512) != 0) /* Set R/W block length to 512 */
  265. ty = 0;
  266. }
  267. }
  268. CardType = ty;
  269. deselect();
  270. if (ty) { /* Initialization succeded */
  271. Stat &= ~STA_NOINIT; /* Clear STA_NOINIT */
  272. FCLK_FAST();
  273. } else { /* Initialization failed */
  274. power_off();
  275. }
  276. return Stat;
  277. }
  278. /*-----------------------------------------------------------------------*/
  279. /* Get Disk Status */
  280. /*-----------------------------------------------------------------------*/
  281. DSTATUS disk_status (
  282. BYTE drv /* Physical drive nmuber (0) */
  283. )
  284. {
  285. if (drv) return STA_NOINIT | STA_NODISK; /* Supports only single drive */
  286. return Stat;
  287. }
  288. /*-----------------------------------------------------------------------*/
  289. /* Read Sector(s) */
  290. /*-----------------------------------------------------------------------*/
  291. DRESULT disk_read (
  292. BYTE drv, /* Physical drive nmuber (0) */
  293. BYTE *buff, /* Pointer to the data buffer to store read data */
  294. DWORD sector, /* Start sector number (LBA) */
  295. UINT count /* Sector count (1..255) */
  296. )
  297. {
  298. if (drv || !count) return RES_PARERR;
  299. if (Stat & STA_NOINIT) return RES_NOTRDY;
  300. if (!(CardType & CT_BLOCK)) sector *= 512; /* Convert to byte address if needed */
  301. if (count == 1) { /* Single block read */
  302. if ((send_cmd(CMD17, sector) == 0) /* READ_SINGLE_BLOCK */
  303. && rcvr_datablock(buff, 512))
  304. count = 0;
  305. }
  306. else { /* Multiple block read */
  307. if (send_cmd(CMD18, sector) == 0) { /* READ_MULTIPLE_BLOCK */
  308. do {
  309. if (!rcvr_datablock(buff, 512)) break;
  310. buff += 512;
  311. } while (--count);
  312. send_cmd(CMD12, 0); /* STOP_TRANSMISSION */
  313. }
  314. }
  315. deselect();
  316. return count ? RES_ERROR : RES_OK;
  317. }
  318. /*-----------------------------------------------------------------------*/
  319. /* Write Sector(s) */
  320. /*-----------------------------------------------------------------------*/
  321. DRESULT disk_write (
  322. BYTE drv, /* Physical drive nmuber (0) */
  323. const BYTE *buff, /* Pointer to the data to be written */
  324. DWORD sector, /* Start sector number (LBA) */
  325. UINT count /* Sector count (1..255) */
  326. )
  327. {
  328. if (drv || !count) return RES_PARERR;
  329. if (Stat & STA_NOINIT) return RES_NOTRDY;
  330. if (Stat & STA_PROTECT) return RES_WRPRT;
  331. if (!(CardType & CT_BLOCK)) sector *= 512; /* Convert to byte address if needed */
  332. if (count == 1) { /* Single block write */
  333. if ((send_cmd(CMD24, sector) == 0) /* WRITE_BLOCK */
  334. && xmit_datablock(buff, 0xFE))
  335. count = 0;
  336. }
  337. else { /* Multiple block write */
  338. if (CardType & CT_SDC) send_cmd(ACMD23, count);
  339. if (send_cmd(CMD25, sector) == 0) { /* WRITE_MULTIPLE_BLOCK */
  340. do {
  341. if (!xmit_datablock(buff, 0xFC)) break;
  342. buff += 512;
  343. } while (--count);
  344. if (!xmit_datablock(0, 0xFD)) /* STOP_TRAN token */
  345. count = 1;
  346. }
  347. }
  348. deselect();
  349. return count ? RES_ERROR : RES_OK;
  350. }
  351. /*-----------------------------------------------------------------------*/
  352. /* Miscellaneous Functions */
  353. /*-----------------------------------------------------------------------*/
  354. DRESULT disk_ioctl (
  355. BYTE drv, /* Physical drive nmuber (0) */
  356. BYTE ctrl, /* Control code */
  357. void *buff __attribute((unused)) /* Buffer to send/receive control data */
  358. )
  359. {
  360. DRESULT res;
  361. if (drv) return RES_PARERR;
  362. buff = 0;
  363. if (ctrl == CTRL_POWER) {
  364. power_off();
  365. return RES_OK;
  366. }
  367. if (Stat & STA_NOINIT) return RES_NOTRDY;
  368. res = RES_ERROR;
  369. switch (ctrl) {
  370. case CTRL_SYNC :
  371. if (select()) {
  372. deselect();
  373. res = RES_OK;
  374. }
  375. break;
  376. default:
  377. res = RES_PARERR;
  378. }
  379. deselect();
  380. return res;
  381. }
  382. /*-----------------------------------------------------------------------*/
  383. /* Device Timer Interrupt Procedure */
  384. /*-----------------------------------------------------------------------*/
  385. /* This function must be called in period of 10ms */
  386. void disk_timerproc (void)
  387. {
  388. BYTE n, s;
  389. n = Timer1; /* 100Hz decrement timer */
  390. if (n) Timer1 = --n;
  391. n = Timer2;
  392. if (n) Timer2 = --n;
  393. s = Stat;
  394. if (SOCKWP) /* Write protected */
  395. s |= STA_PROTECT;
  396. else /* Write enabled */
  397. s &= ~STA_PROTECT;
  398. if (SOCKINS) /* Card inserted */
  399. s &= ~STA_NODISK;
  400. else /* Socket empty */
  401. s |= (STA_NODISK | STA_NOINIT);
  402. Stat = s; /* Update MMC status */
  403. }